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 Features
* Pixel Size: 13 m x 13 m (13 m pitch) * High Data Output Rate: 20 MHz typ * High Responsivity and Resolution over a Wide Spectral Range: from Blue (400 nm) up
to Near Infrared (1100 nm)
* Improved Dark Signal and Photo Response Uniformity * Low Temporal Noise and High Dynamic Range: Over 6000/1 * Ease and Flexibility of Operation:
- Only two External Basic Drive Clocks - Internal or External Sample and Reset Clocks * 24-lead DIL Package
Pin Identification
Pin Number 1 2 3 4 8 9 10 11 12 13 15 16 17 18 19 21 22 23 24 5, 6, 7, 14, 20 Symbol VOSA ECHA SECHA RA VDD TP3 TP2 VT TP1 VSS P T VGS RB VINH SECHB ECHB VOSB VDR DNC Designation Video Output Signal A (Odd Channel) A Channel Sample-and-hold Gate Input A Channel Internal Sample Clock-output A Channel External Reset Clock Input Output Amplifier Drain And Internal Logic Supply Test Point 3 Test Point 2 Register And Photosensitive Zone DC Bias Test Point 1 Substrate Bias (Ground) Transfer Clock Register Transport Clock Output Gate DC Bias B Channel External Reset Clock Input Internal Sample Clock Inhibition B Channel Internal Sample Clock Input B Channel Sample-and-hold Gate Input Video Output Signal B (Even Channel) Reset DC Bias Do Not Connected
VOSA ECHA S ECHA RA DNC DNC DNC VDD TP3 TP2 VT TP1 1 24 2 23 3 22 4 21 5 20 6 19 TH7804A 7 18 8 17 9 16 10 15 11 14 12 13 VDR VOSB ECHB S ECHB DNC VINH RB VGS T P DNC VSS
Linear Charged Couple Device (CCD) Image Sensor 1024 Pixels TH7804A
Rev. 1989A-IMAGE-05/02
1
Absolute Maximum Ratings*
Storage Temperature ..................................... -55C to +150C Operating Temperature....................................... 0C to +70C Thermal Cycling..........................................................15C/mn Maximum Voltage: * Pins: 2, 4, 8,12,15,16,18,19, 22, 24 ................-0.3V to +18V * Pins: 9,10,11,17 .............................................. -0.3V to +18V * Pin: 13 .............................................................................. 0V *NOTICE: Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Operating Range Operating Precautions
The operating range defines the temperature limits between which functionality is guaranteed: 0C to 70C. Shorting the video output to VSS or VDD, even temporarily, can permanently damage the output amplifier.
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TH7804A
Operating Conditions (T = 25)
Table 1. DC Bias Characteristics
Value Parameter Output Amplifier Drain Supply Reset DC Bias Output Gate DC Bias Photosensitive Zone And Register DC Bias Substrate Bias Test Point 1 Tests Points 2 And 3 Notes: Symbol VDD VDR VGS VT VSS TP1 TP2, TP3 Min. 14 VDD - 2.4 5.5 0.95 VTN 0.0 Typ. 15 VDD - 2 6 VTN 0.0 VDD VSS Max 16 VDD - 1 6.5 1.05 V TN Unit V V V V V V V
(2) (2) (1)
Remark
1. Nominal value of VT: VTN = 6.7V if T clock levels are at their typical value. 2. No use for operation. For testing purpose only. V = ( VT )HIGH + ( VT )LOW 5% ---------------------------------------------------------------------2
TN
Basic Internal Configuration
SECHA and RA SECHB and RA internal to TH7804A
Table 2. Selection of Nominal Mode
Option Internal Sampling Internal Reset Note: Implementation VINH (19) Connected to VSS SECHA (3) and ECHA (2) Strapped SECHB (21) and ECHB (22) Strapped RA (4) and RB (18) Connected to VDD Remarks
(1)
see note
1. Make the straps as short as possible to avoid any parasitic coupling to these connections. The load capacitance introduced by the strap should not exceed 5 pF.
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1989A-IMAGE-05/02
Figure 1. Basic Test Configuration
Figure 2. Timing Diagram in Basic Mode
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1989A-IMAGE-05/02
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Table 3. Drive Clock Characteristics (see Figure 2)
Value Parameter Transfer Clock Register Transport Clock Register Transport Clock Capacitance Transfer Clock Capacitance Note: Symbol P, T CT CP Logic High Low Min. 11 0.0 Typ. 13 0.4 400 130 Max. 14 V 0.6 700 200 pF pF Unit Remark
(1)
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal. If such spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically 20 to 100) in the corresponding driver output.
Table 4. Static and Dynamic Electrical Characteristics
Value Parameter DC Output Level Output Impedance Register Single-stage Transfer Efficiency Max. Data Output Frequency Input Current On Pins: 2, 9, 10, 11, 12, 15, 16, 17, 18, 22 Peak Current Sink on T Clock Peak Current Sink on P Clock Output Amplifier + Internal Logic Supply Current Static Power Dissipation Notes: Symbol VREF ZS CTE FS max Ie (IT)P (IP)P IDD PD 250 80 17 255 300 99.992 12 Min. 8 Typ. 10 500 99.998 20 2 Max. 12 Logic V % MHz A mA mA mA mW VOS = 1V (1)
(2)
Remark
VIN = 15V All other pins: 0V tRISE = 15 ns tRISE = 15 ns VINH = 0V VDD = 15V VINH = 0V VDD = 15V
1. VOS = average video output voltage. 2. Fs = 2 F T. The minimum clock frequency is limited by the increase in dark signal.
Electro-optical Performance
General measurement conditions: TC = 25C; Ti = 1 ms; FT = 2.5 MHz (FDATA = 5 MHz) Light source: tungsten filament lamp (2854 K) + B6 38 filter (2 mm thick), F/3.5 aperture. The filter limits the spectrum to 700 nm; in these conditions 1J/cm2 corresponds to 3.5 lux.s. Operating conditions (see Figure 1). First and last pixels, as well as reference elements, are excluded from the specification. Measurements taken on each output in succession.
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1989A-IMAGE-05/02
Table 5. Electro-optical Performance
Value Parameter Saturation Output Voltage Saturation Exposure Responsivity Responsivity Unbalance Photo Response Non-uniformity Peak-to-peak Contrast Transfer Function at FN (38 I p/mm) Temporal Noise In Darkness Dynamic Range (Relative to rms Noise) Average Dark Signal Dark Signal Non-uniformity Peak-to-peak Notes: DR VDS DSNU 4000 Symbol VSAT ESAT R R/R PRNU CTF 4.5 Min. 1.3 Typ. 1.8 0.30 6 2 3 70 180 6000 0.08 0.15 0.5 0.5 mV mV 8 10 Max. 2.3 Unit V J/cm2 V/J/cm2 % % VOS % Vrms
(3)
Remark
(1) (2)
VOS = 50 mV to 1V VOS = 0.9V
(4)
1. Value measured with respect to zero reference level (see Figure 2). 2. Conversion factor is typically 1.5 V/e-. 3. R/R is defined as 200 RA - RB ---------------------------------RA + RB where RA is responsivity of video output A, RB is responsivity of video output B. 4. Measured in Correlated Double Sampling (C.D.S.) mode.
Figure 3. Typical Spectral Response
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TH7804A
Figure 4. CTF Typical Curves (2854 K Source)
Electro-optical Performance Without Infrared Cut-off Filtering
The TH7804A's special semiconductor process enables it to exploit the silicon's high near infrared sensitivity while maintaining good imaging performance in terms of response uniformity and resolution. Typical changes in performance with and without IR filtering are summarized below.
With IR Cut-off Filter Average Video Signal Due to a Given Scene Illumination PRNU (Single Defects Excluded) CTF at Nyquist Frequency VOS 5% 70%
No IR Cut-off Filter VOS x 4 5% 50%
Complementary Operating Modes
TH7804A may be used in several configurations in regards to video output sampling and charge sensing reset. 1. Sampling Options: Inhibition of internal sampling pulses allows for two possibilities: a. no sampling: video output delivered in unsampled form, b. sampling by external clocks: external sampling pulses directly applied to
ECHA, ECHB inputs.
If internal sampling clocks S ECHA and SECHB are not used, it is recommended of unpower the corresponding clock drivers, as this will greatly reduce on-chip power consumption. 2. External Reset Option: The position and period of the charge reset clocks may be optimized by using external clocks on RA and RB inputs. This is specially interesting to optimize the video outputs for Correlated Double Sampling (in order to reduce noise and improve S/N ratio). Control signals to be applied in the different configurations are shown in Table 6.
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1989A-IMAGE-05/02
Table 6. Selection of Operating Modes
Option No Sampling Implementation ECHA (2) and ECHB (22) connected to VDD SECHA (3) and SECHB (21) unconnected VINH (19) connected to VDD Sampling clocks connected to ECHA ECHB SECHA and SECHB unconnected VINH (19) connected to VDD Ext. RA on RA (4) input Ext. RB on RB (18) Remarks
(1)
Sampling by External Clocks
see Figure 5 for sampling clock timing
(1)
Reset Control by External Clocks Note:
see Figure 4 for reset clock timing
1. Drain supply current IDD decreases from 10 mA to 8 mA typically when internal sampling clock is disabled.
Table 7. External RA, RB, ECHA, ECHB Clock Characteristics
Values Parameter External Reset Clock Sampling Clocks Reset and Sampling Clock Capacitance Symbol RA, RB ECHA, ECHB CRA, CRB CECHA, CECHB Logic High Low Min. 12 0.0 Typ. 12.5 0.4 10 Max. 13 0.6 15 Unit V V pF
Insertion of a serial resistor (typically 100) at the driver output avoids spurious negative transients.
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Figure 5. Timing Diagram -- Clocks and Video Output Timing Diagram With and Without On-chip Sampling.
External reset clocks improve electro-optical performance, as listed below. Other operating conditions and other electrooptical parameters remain unchanged. Table 8. Performance Improvements with External RA and RB Configuration
Value Parameter Saturation Output Voltage Responsivity Dynamic Range Symbol VSAT R DR Typ. 2.0 8 8000 Unit V V/J/cm2
Electro-optical performances obtained with complementary modes are not guaranteed for the standard products.
9
1989A-IMAGE-05/02
Outline Drawing
Z = 1.28 0.23
2.16
Notes:
1. If an optical reference is needed, it is recommended to use the window face plane. 2. Variation of Z (azimuth) on the photosensitive area of a device is 0.1 mm. 3. Value and tolerance of Y are applicable to each individual pixel of the photosensitive line.
Ordering Code
TH7804ACC
10
TH7804A
1989A-IMAGE-05/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
1989A-IMAGE-05/02 0M


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